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  october 2016 docid026183 rev 2 1 / 18 this is information on a product in full production. www.st.com stp7n105k5, stu7n105k5, STW7N105K5 n - channel 1050 v, 1.4 typ., 4 a mdmesh? k5 power mosfets in to - 220, ipak and to - 247 packages datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d p tot stp7n105k5 1050 v 2 4 a 110 w stu7n105k5 STW7N105K5 ? industrys lowest r ds(on) x area ? industrys best fom (figure of merit) ? ultra - low gate charge ? 100% avalanche tested ? zener - protected applications ? switching applications description this very high voltage n - channel power mosfet is d esigned using mdmesh? k5 technology based on an innovative proprietary vertical structure. the result is a dramatic reduction in on - resistance and ultra - low gate charge for applications requiring superior power density and high efficiency. table 1: device summary order code marking package packaging stp7n105k5 7n105k5 to - 220 tube stu7n105k5 ipak STW7N105K5 to - 247 1 2 3 t o-247 1 2 3 tab t o-220 i p ak tab 1 2 3 d(2, t ab) g(1) s(3) am01476v1
contents stp7n105k5, stu7n105k5, STW7N105K5 2 / 18 docid026183 rev 2 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 2.1 electrical characteri stics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 9 4 package information ................................ ................................ ..... 10 4.1 to - 220 package information ................................ ........................... 11 4.2 ipak package inform ation ................................ ............................... 13 4.3 to - 247 package information ................................ ........................... 15 5 revision history ................................ ................................ ............ 17
stp7n105k5, stu7n105k5, STW7N105K5 electrical ratings docid026183 rev 2 3 / 18 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 30 v i d drain current (continuous) at t c = 25 c 4 a i d drain current (continuous) at t c = 100 c 3 a i dm (1) drain current (pulsed) 16 a p tot total dissipation at t c = 25 c 110 w i ar avalanche current, repetitive or not repetitive (pulse width limited by t jmax ) 1.5 a e as single pulse avalanche energy (starting t j = 25 c, i d =i ar , v dd = 50 v) 132 mj dv/dt (2) peak diode recovery voltage slope 4.5 v/ns dv/dt (3) mosfet dv/dt ruggedness 50 v/ns t j operating junction temperature range - 55 to 150 c t stg storage temperature range notes: (1) pulse width limited by safe operating area. (2) i sd 4 a, di/dt 100 a/s, v ds(peak) v (br)dss ; v sd 840 v (3) v ds 840 v table 3: thermal data symbol parameter value unit to - 220 ipak to - 247 r thj - case thermal resistance junction - case max 1.14 c/w r thj - amb thermal resistance junction - amb max 62.5 100 50 c/w
electrical characteristics stp7n105k5, stu7n105k5, STW7N105K5 4 / 18 docid026183 rev 2 2 electrical characteristics (t case = 25 c unless otherwise specified). table 4: on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltag e v gs = 0, i d = 1 ma 1050 v i dss zero gate voltage drain current v gs = 0, v ds = 1050 v 1 a v gs = 0, v ds = 1050 v, tc=125 c (1) 50 a i gss gate body leakage current v ds = 0, v gs = 20 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 3 4 5 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 2 a 1.4 2 notes: (1) defined by design, not subject to production test. table 5: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds =100 v, f=1 mhz, v gs =0 - 380 - pf c oss output capacitance - 40 - pf c rss reverse transfer capacitance - 0.65 - pf c o(tr) (1) equivalent capacitance time related v gs = 0, v ds = 0 to 840 v - 47 - pf c o(er) (2) equivalent capacitance energy related - 17 - pf r g intrinsic gate resistance f = 1mhz open drain - 7 - q g total gate charge v dd = 840 v, i d = 4 a v gs =10 v figure 18: "test circuit for gate charge behavior" - 11 - nc q gs gate - source charge - 2.8 - nc q gd gate - drain charge - 5.6 - nc notes: (1) time related is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss (2) energy related is defined as a constant equivalent capacitance giving the same stored energy as c oss when v ds increases from 0 to 80% v dss
stp7n105k5, stu7n105k5, STW7N105K5 electrical characteristics docid026183 rev 2 5 / 18 table 6: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 525v, i d = 2 a, r g =4.7 , v gs =10 v (see figure 17: "test circuit for resistive load switching times" and figure 22: "switching time waveform" ) - 17.5 - ns t r rise time - 7 - ns t d(off) turn - off delay time - 43 - ns t f fall time - 25 - ns table 7: source drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 4 a i sdm source - drain current (pulsed) 16 a v sd (1) forward on voltage i sd = 4 a, v gs =0 - 1.6 v t rr reverse recovery time i sd = 4 a, v dd = 60 v di/dt = 100 a/s, figure 19: "test circuit for inductive load switching and diode recovery times" - 370 ns q rr reverse recovery charge - 3 c i rrm reverse recovery current - 16.5 a t rr reverse recovery time i sd = 4 a,v dd = 60 v di/dt=100 a/s, tj=150 c figure 19: "test circuit for inductive load switching and diode recovery times" - 600 ns q rr reverse recovery charge - 4.4 c i rrm reverse recovery current - 14.5 a notes: (1) pulsed: pulse duration = 300s, duty cycle 1.5% table 8: gate - source zener diode symbol parameter test conditions min typ. max. unit v (br)gso gate - source breakdown voltage i gs = 1ma, i d =0 30 - - v the built - in back - to - back zener diodes are specifically designed to enhance the esd performance of the device. the zener voltage facilitates efficient and cost - effective device integrity protection, thus eliminating the need for additional external componentry.
electrical characteristics stp7n105k5, stu7n105k5, STW7N105K5 6 / 18 docid026183 rev 2 2.1 electrical characteristics (curves) figure 2 : safe operating area for to - 220 and to - 247 figure 3 : thermal impedance for to - 220 and to - 247 figure 4 : safe operating area for ipak figure 5 : thermal impedance for ipak figure 6 : output characteristics figure 7 : transfer characteristics r on li m i t cg20930 t p z th = k r thj-c = t p / ? 10 -5 10 -4 10 -3 10 -2 10 -2 10 -1 k 10 -1 t p (s) ? = 0.5 = 0.2 = 0.1 = 0.01 = 0.02 = 0.05 single pulse z th = k r thj-c = t p / ? t p ?
stp7n105k5, stu7n105k5, STW7N105K5 electric al characteristics docid026183 rev 2 7 / 18 figure 8 : gate charge vs gate - source voltage figure 9 : static drain - source on - resistance figure 10 : capacitance variations figure 11 : source - drain diode forward characteristics figure 12 : normalized gate threshold voltage vs temp erature figure 13 : normalized on - resistance vs temperature
electrical characteristics stp7n105k5, stu7n105k5, STW7N105K5 8 / 18 docid026183 rev 2 figure 14 : normalized v(br)dss vs temperature figure 15 : maximum avalanche energy vs starting tj figure 16 : output capacitance stored energy e as 0 40 t j (c) (mj) 20 100 60 80 0 20 40 60 80 120 140 100 120 i d =1.5 a v dd =50 v gipg210320141421s a
stp7n105k5, stu7n105k5, STW7N105K5 test circuits docid026183 rev 2 9 / 18 3 test circuits figure 17 : test circuit for resistive load switching times figure 18 : test circuit for gate charge behavior figure 19 : test circuit for inductive load switching and diode recovery times figure 20 : unclamped inductive load test circuit figure 21 : unclamped inductive waveform figure 22 : switching time waveform
package information stp7n105k5, stu7n105k5, STW7N105K5 10 / 18 docid026183 rev 2 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at : www.st.com . ecopack ? is an st trademark.
stp7n105k5, stu7n105k5, STW7N105K5 package information docid026183 rev 2 11 / 18 4.1 to - 220 package information figure 23 : to - 220 type a package outline
package information stp7n105k5, stu7n105k5, STW7N105K5 12 / 18 docid026183 rev 2 table 9: to - 220 type a mechanical data dim. mm min. typ. max. a 4.40 4.60 b 0.61 0.88 b1 1.14 1.55 c 0.48 0.70 d 15.25 15.75 d1 1.27 e 10.00 10.40 e 2.40 2.70 e1 4.95 5.15 f 1.23 1.32 h1 6.20 6.60 j1 2.40 2.72 l 13.00 14.00 l1 3.50 3.93 l20 16.40 l30 28.90 ?p 3.75 3.85 q 2.65 2.95
stp7n105k5, stu7n105k5, STW7N105K5 package information docid026183 rev 2 13 / 18 4.2 ipak package information figure 24 : ipak (to - 251) type a package outline
package information stp7n105k5, stu7n105k5, STW7N105K5 14 / 18 docid026183 rev 2 table 10: ipak (to - 251) type a package mechanical data dim. mm min. typ. max. a 2.20 2.40 a1 0.90 1.10 b 0.64 0.90 b2 0.95 b4 5.20 5.40 b5 0.30 c 0.45 0.60 c2 0.48 0.60 d 6.00 6.20 e 6.40 6.60 e 2.28 e1 4.40 4.60 h 16.10 l 9.00 9.40 l1 0.80 1.20 l2 0.80 1.00 v1 10
stp7n105k5, stu7n105k5, STW7N105K5 package information docid026183 rev 2 15 / 18 4.3 to - 247 package information figure 25 : to - 247 package outline
package information stp7n105k5, stu7n105k5, STW7N105K5 16 / 18 docid026183 rev 2 table 11: to - 247 package mechanical data dim. mm min. typ. max. a 4.85 5.15 a1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 d 19.85 20.15 e 15.45 15.75 e 5.30 5.45 5.60 l 14.20 14.80 l1 3.70 4.30 l2 18.50 ?p 3.55 3.65 ?r 4.50 5.50 s 5.30 5.50 5.70
stp7n105k5, stu7n105k5, STW7N105K5 revision history docid026183 rev 2 17 / 18 5 revision history table 12: document revision history date revision changes 07 - apr - 2014 1 first release. 17 - oct - 2016 2 updated figure 8: "gate charge vs gate - source voltage" and table 5: "dynamic" . minor text changes.
stp7n105k5, stu7n105k5, STW7N105K5 18 / 18 docid026183 rev 2 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved


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